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| CY24130 HOTLink IITM SMPTE Receiver Training Clock Features Benefits Integrated phase-locked loop Low-jitter, high-accuracy outputs 3.3V operation Internal PLL with up to 400-MHz internal operation Meets critical timing requirements in complex system designs Enables application compatibility Table 1. Frequency table Part Number CY24130-1 CY24130-2 Outputs 2 2 Input Frequency 27 MHz (Driven Reference) 27 MHz (Crystal Reference) Output Frequency Range 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) Logic Block Diagram XIN XOUT P PLL REFCLK S0 S1 S2 OSC. Q VCO OUTPUT MULTIPLEXER AND DIVIDERS CLKA VDDL VDD AVDD AVSS VSS VSSL Table 2. Frequency Select Options S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CLKA 27 36 54 148.50 74.25 OFF, pulled low OFF, pulled low OFF, pulled low REFCLK 27 27 27 27 27 27 27 27 Units MHz MHz MHz MHz MHz MHz MHz MHz Cypress Semiconductor Corporation Document #: 38-07711 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 22, 2008 [+] Feedback CY24130 Pin Configuration Figure 1. CY24130-1, -2, 16-pin TSSOP XIN VDD AVDD S0 AVSS VSSL N/C CLKA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT S2 REFCLK VSS N/C VDDL S1 N/C Table 3. Pin Definition Name XIN VDD AVDD S0 AVSS VSSL N/C CLKA N/C S1 VDDL N/C VSS REFCLK S2 XOUT Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Reference Crystal Input. Voltage Supply. Analog Voltage Supply. Frequency Select 0. Analog Ground. VDDL Ground. No Connect. 27-/36-/54-/148.50-/74.25-MHz Clock Output (frequency selectable). No Connect. Frequency Select 1. Voltage Supply. No Connect. Ground. Reference Clock Output. Frequency Select 2. Reference Crystal Output. Leave floating for -1. Absolute Maximum Conditions Parameter VDD, AVDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Electro-Static Discharge Min. -0.5 - - AVSS - 0.3 2 Max. 7.0 7.0 125 AVDD + 0.3 - Unit V V C V kV Recommended Operating Conditions Parameter VDD/AVDDL/VDDL TA CLOAD fREF CLNOM Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Nominal Parallel Crystal Load Capacitance for -2 Min. 3.135 0 - - - Typ. 3.3 - - 27 18 Max. 3.465 70 15 - - Unit V C pF MHz pF Document #: 38-07711 Rev. *A Page 2 of 6 [+] Feedback CY24130 DC Electrical Specifications Parameter[1] IOH IOL IIH IIL VIH VIL IVDD IVDDL Name Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VIH = VDD VIL = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current Min. 12 12 - - 0.7 - - - Typ. 24 24 5 - - - 16 14 Max. - - 10 10 - 0.3 - - Unit mA mA A A V V mA mA AC Electrical Specifications Parameter[1] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Figure 2. Test and Measurement Setup VDDs 0.1 F DUT Outputs CLOAD Description Duty Cycle is defined in Figure 3; t1/t2, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 4. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 4. CLKA Peak-Peak Period Jitter Min. 45 0.8 0.8 - - Typ. 50 1.4 1.4 100 - Max. 55 - - - 3 Unit % V/ns V/ns ps ms GND Voltage and Timing Definitions Figure 3. Duty Cycle Definitions t1 t2 VDD 50% of VDD Clock Output 0V Note 1. Not 100% tested. Document #: 38-07711 Rev. *A Page 3 of 6 [+] Feedback CY24130 Figure 4. t3 ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t4 V DD 80% of V DD 20% of V DD 0V Clock Output Ordering Information Ordering Code Pb-free CY24130ZXC-1[2] CY24130ZXC-1T [2] Package Type 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V CY24130ZXC-2[2] CY24130ZXC-2T [2] CY24130KZXC-1 CY24130KZXC-1T Note 2. Not recommended for new design. Document #: 38-07711 Rev. *A Page 4 of 6 [+] Feedback CY24130 Package Drawing and Dimensions Figure 5. 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] 51-85091-*A Document #: 38-07711 Rev. *A Page 5 of 6 [+] Feedback CY24130 Document History Page Document Title: CY24130 HOTLink IITM SMPTE Receiver Training Clock Document Number: 38-07711 REV. ** *A ECN NO. 314514 2442066 Orig. of Change RGL AESA Submission Date See ECN See ECN New Data Sheet Updated template. Added Note "Not recommended for new designs." Added part number CY24130KZXC-1, and CY24130KZXC-1T in ordering information table. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07711 Rev. *A Revised May 22, 2008 Page 6 of 6 MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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